Mississippi State University
Date of Degree
Graduate Thesis - Open Access
Master of Science
James Worth Bagley College of Engineering
Department of Electrical and Computer Engineering
During the last two decades, the performance of CPU has been developed much faster than that of memory. In order to reduce the performance gap between CPU and memory, cache memories should have been used between CPU and memory. In general, cache memory is a small and fast buffer to reduce memory access time by saving data in advance before CPU uses. There are two types of cache memory: instruction cache and data cache. In addition, there can be multi-levels (Level 1, 2, ?etc) in memory hierarchy (memory and cache memories) for system purpose: the level 1 (on-chip) cache is the closest one to CPU and it affects system performance directly. In this study, we evaluated two factors in designing an efficient Level 1 data cache. Those factors are: distance between two data in an array and multi xor mapping functions in a bank. We designed a data cache called SLDC (Store/Load Dependent Cache, Two-way) to implement the first factor. This cache uses the distance between two data addresses of data-transfer instructions (load and store). It groups close data into the same group and places into the same bank. The other cache we designed for the second factor is called Multi-XOR (MXOR). The MXOR splits the cache virtually into several zones (2 to 6 areas); a different xor mapping function per area is used to index data (for better cache utilization). In this study, we used the SimpleScalar simulation program to implement data cache with SPEC2000FP benchmark programs. Based on the experiment results, we recommended considering those factors in designing an efficient cache memory since SLDC and MXOR show some improvement (5-to-10%) compared to a conventional cache memory (two-way set-associative).
Ammari, Rami J., "A Study for Reducing Conflict Misses in Data Cache" (2004). Theses and Dissertations. 268.