Theses and Dissertations

Issuing Body

Mississippi State University


Reese, Robert B.

Committee Member

Bruce, Jerry W.

Committee Member

Harden, James C.

Committee Member

Philip, Thomas

Date of Degree


Document Type

Dissertation - Open Access


Computer Engineering

Degree Name

Doctor of Philosophy


James Worth Bagley College of Engineering


Department of Electrical and Computer Engineering


The use of computer aided design (CAD) tools has catalyzed the growth of IC design techniques. The rapid growth in transistor count for synchronous digital circuits has increased circuit complexity. This growing complexity of synchronous circuits has exposed design issues such as clock skew, increased power consumption, increased electromagnetic interference and worst case performance. The increasing number of challenges posed by synchronous designs has encouraged researchers to explore asynchronous design techniques as an alternative methodology. Asynchronous circuits do not use a global clock signal that is the primary cause of many design challenges faced by synchronous designers. It has also been shown in some designs that asynchronous circuits consumes less power, and exhibits better average case performance than synchronous circuits. Asynchronous design techniques, even with their various advantages over synchronous systems, are not widely accepted by logic designers. This is due to the shortcomings of asynchronous design methodologies, primarily, the limited availability of CAD tool support and the use of proprietary specification languages. To overcome the shortcomings of current asynchronous design techniques, this research uses a methodology for designing asynchronous circuits starting from clocked RTL design. This research extends the concepts of Phased Logic (PL) and marked graphs to quasi-delay insensitive gates (QDI) gates to create an asynchronous PL-QDI methodology. The PL methodology is easy to use as it maps conventional RTL designs into delay insensitive PL circuits using commercial CAD tools. Caltech?s QDI gates exhibit fast forward latency, but the use of Caltech?s methodology requires a user skilled in the pecurialities of the Caltech design methodology. This research uses best of Caltech?s QDI circuit methodology and the PL methodology to come up with a new asynchronous PL-QDI methodology. It also presents a synthesis algorithm that uses commercially available synchronous CAD tools to map clocked designs to PL-QDI systems. Results of this research show that third-party clocked RTL codes including intellectual property (IP) cores can be converted to asynchronous PL-QDI systems using the PL-QDI CAD tools presented in this research. This work shows how mature synchronous CAD tools can be used to design clockless circuits.