Theses and Dissertations
Issuing Body
Mississippi State University
Advisor
Reese, B. Robert
Committee Member
Winton, S. Raymond
Committee Member
Koshka, Yaroslav
Date of Degree
5-2-2009
Document Type
Graduate Thesis - Open Access
Major
Electrical Engineering
Degree Name
Master of Science
College
James Worth Bagley College of Engineering
Department
Department of Electrical and Computer Engineering
Abstract
On-chip supply voltage fluctuations are known to adversely affect performance parameters of VLSI circuits. These power supply fluctuations reduce drive capability, causes reliability issues, decrease noise margin and also adversely affect timing. Technology scaling further aggravates the problem as IR and Ldi/dt noise sources increase with each device generation. Current method used to reduce power supply variations uses an on-chip decoupling capacitors (decaps). These MOS capacitors utilize significant die area with about 15%-20% common for high-end microprocessors [4]. They also consume a considerable amount of power due to leakage and are prone to oxide breakdown during an ESD event because of reduced oxide thickness, making MOS capacitors unsuitable for technologies 90 nm and below. To improve the effectiveness of decap and reduce decap’s area, a new active decap design is proposed for 90 nm technology.
URI
https://hdl.handle.net/11668/15145
Recommended Citation
Thirumalai, Rooban Venkatesh K G, "Power supply noise reduction in 90 nm using active decap" (2009). Theses and Dissertations. 3587.
https://scholarsjunction.msstate.edu/td/3587
Comments
POWER SUPPLY NOISE||NOISE REDUCTION||ACTIVE DECAP||DECOUPLING CAPACITOR