Reese, B. Robert
Winton, S. Raymond
Date of Degree
Graduate Thesis - Open Access
Master of Science
James Worth Bagley College of Engineering
On-chip supply voltage fluctuations are known to adversely affect performance parameters of VLSI circuits. These power supply fluctuations reduce drive capability, causes reliability issues, decrease noise margin and also adversely affect timing. Technology scaling further aggravates the problem as IR and Ldi/dt noise sources increase with each device generation. Current method used to reduce power supply variations uses an on-chip decoupling capacitors (decaps). These MOS capacitors utilize significant die area with about 15%-20% common for high-end microprocessors . They also consume a considerable amount of power due to leakage and are prone to oxide breakdown during an ESD event because of reduced oxide thickness, making MOS capacitors unsuitable for technologies 90 nm and below. To improve the effectiveness of decap and reduce decap’s area, a new active decap design is proposed for 90 nm technology.
Thirumalai, Rooban Venkatesh K G, "Power supply noise reduction in 90 nm using active decap" (2009). Theses and Dissertations MSU. 3587.