Theses and Dissertations
Issuing Body
Mississippi State University
Advisor
Dandass, Yongindeer
Committee Member
Bruce, J.W.
Committee Member
Reese, Robert
Date of Degree
5-3-2008
Document Type
Graduate Thesis - Open Access
Major
Computer Engineering
Degree Name
Master of Science
College
James Worth Bagley College of Engineering
Department
Department of Electrical and Computer Engineering
Abstract
Reconfigurable computing has the potential for providing significant performance increases to a number of computing applications. However, realizing these benefits requires digital design experience and knowledge of hardware description languages (HDLs). While a number of tools have focused on translation of high-level languages (HLLs) to HDLs, the tools do not always create optimized digital designs that are competitive with hand-coded solutions. This work describes an automatic optimization in the C-to-HDL transformation that reorganizes operations between pipeline stages in order to reduce critical path lengths. The effects of this optimization are examined on the MD5, SHA-1, and Smith-Waterman algorithms. Results show that the optimization results in performance gains of 13%-37% and that the automatically-generated implementations perform comparably to hand-coded implementations.
URI
https://hdl.handle.net/11668/15104
Recommended Citation
Holland, Wesley James, "A framework for automatically generating optimized digital designs from C-language loops" (2008). Theses and Dissertations. 130.
https://scholarsjunction.msstate.edu/td/130