Theses and Dissertations
Issuing Body
Mississippi State University
Advisor
Ginn, Herbert L.
Committee Member
Davis, Justin
Committee Member
Follett, Randolph
Date of Degree
5-5-2007
Document Type
Graduate Thesis - Open Access
Major
Electrical Engineering
Degree Name
Master of Science
College
James Worth Bagley College of Engineering
Department
Department of Electrical and Computer Engineering
Abstract
Most digital control architectures for power system applications require synchronization with the distribution system voltage. Therefore, a phase-locked loop (PLL), implemented in a DSP, is generally among the digital control blocks of the control system. The PLL analyzes the bus voltage and provides power system information for some of the other blocks to do further calculation. Thus, the performance of the PLL has a broad impact on the system performance. Small-scale power systems, such as naval systems, pose a challenging environment for PLL design due to voltage distortion and variation in the fundamental frequency that is large as compared to large terrestrial systems. Our objective is to improve the accuracy of the PLL digital block and hence enhance the digital control system. This research compares two PLL algorithms, as well as the use of a PI controller or lag controller with respect to their steady state and transient performance.
URI
https://hdl.handle.net/11668/17411
Recommended Citation
Huang, Qinghua, "Digital Phase-Locked Loop Design for Naval Applications" (2007). Theses and Dissertations. 1508.
https://scholarsjunction.msstate.edu/td/1508