Theses and Dissertations
Issuing Body
Mississippi State University
Advisor
Reese, Robert
Committee Member
Jones, Bryan A.
Committee Member
Bruce, J.W.
Committee Member
Abdelwahed, Sherif
Date of Degree
5-4-2018
Original embargo terms
MSU Only Indefinitely
Document Type
Dissertation - Campus Access Only
Major
Electrical and Computer Engineering
Degree Name
Doctor of Philosophy
College
James Worth Bagley College of Engineering
Department
Department of Electrical and Computer Engineering
Abstract
Asynchronous design is a possible alternative design methodology that has the ability to alleviate issues associated with clock skew, power dissipation, and process and environmental variability among transistors, issues encountered in typical synchronous design methodologies. This investigation studies the implementation of two asynchronous models of the Texas Instruments MSP430 processor family using a logic system known as Null Convention Logic (NCL). The study also investigates two design styles of NCL: the data-driven and control-driven design styles. This example and others show that although there are tradeoffs in chip area and performance, the control-driven design style is a viable methodology that can lead to designs that are low in energy usage. The openMSP430 processor project is the baseline for the investigation as it is a mature open-source project. Silicon-proven multiple times and fully synthesizable, it parallels the original Texas Instruments family nearly cycle for cycle. UNCLE (Unified NCL Environment) is a toolset used to create comparable implementations of the openMSP430 architecture that are data-driven and control-driven in nature. This investigation shows that the control-driven implementation has a slightly larger chip area due to the complexity of the control path and its effects on the data path. While the control path has a lower area than the data-driven model due to area optimization, the data path of the control-driven version is larger than that of the data-driven model. Because of these issues of complexity in both the control and data paths, the performance of the model suffers as well, degrading from the already poor performance of the traditional data-driven NCL model. Along with the increase in chip area and the decrease in performance, the control-driven model sees a 50.2% average decrease in energy usage as compared to the data-driven model. As with most design choices in engineering, there are tradeoffs when using either design style of NCL. This investigation serves to allow designers to make a well-informed decision when deciding between the two.
URI
https://hdl.handle.net/11668/17453
Recommended Citation
Taylor, Ryan, "Investigation of a Control-Driven Design Style for a 16-Bit Microprocessor Implementation" (2018). Theses and Dissertations. 2829.
https://scholarsjunction.msstate.edu/td/2829
Comments
microprocessor||msp430||data-driven||control-driven||asynchronous circuits||null convention logic