Theses and Dissertations
Issuing Body
Mississippi State University
Advisor
Chu, Yul
Date of Degree
8-11-2007
Document Type
Graduate Thesis - Open Access
Major
Electrical Engineering
Degree Name
Master of Science
College
James Worth Bagley College of Engineering
Department
Department of Electrical and Computer Engineering
Abstract
A Buffer management algorithm plays an important role in determining the packet loss ratio in a computer network. Two types of packet buffer management algorithms, static and dynamic, can be used in a Network Interface Card (NIC) of a network terminal. In general, dynamic algorithms have better efficiency than the static algorithms. However, once the allocated buffer space is filled for an application, further incoming packets for that application get rejected. We propose a history-based scheme called History Based Dynamic Algorithm (HBDA), which reduces packet loss ratio by monitoring whether or not the application is active. For average network traffic loads, the HBDA improves the packet loss ratio by 15.9% and 11% (for load = 0.7) compared to DA and DADT, respectively. For heavy traffic load, improvement is 16.2% and 11.7% (for load = 0.7) and for actual traffic load improvement is 12.7% and 7.1% (for load = 0.7) over DA and DADT respectively. We also developed a new architecture for the Network Interface Card. The new architecture will support the multi-processor system and gives more consideration to the application with the highest priority. It has two control units for processing the incoming packets in parallel. For the traffic mix with average network traffic loads , the new architecture improves the packet loss ratio for priority application by a significant amount.
URI
https://hdl.handle.net/11668/17837
Recommended Citation
Batra, Shalini, "An Efficient Algorithm and Architecture for Network Processors" (2007). Theses and Dissertations. 504.
https://scholarsjunction.msstate.edu/td/504